Image manipulation for wafer plane conformity in optical lithography
|Project members:||prof.dr.ir. M. Verhaegen (Michel), R.I. Mustata, MSc (Ruxandra)|
|Keywords:||Distributed and large-scale systems, Optics and imaging, Model predictive control, Control of high-resolution imaging, Spatial-temporal large-scale systems|
|Sponsored by:||Delft University of Technology, STW, ASML , AAE|
One of the main challenges in semiconductor industry is to continue following Moore's Law towards ever smaller, cheaper, more powerful and energy-efficient chips, thereby improving the performance of electronic devices, including consumer electronics (laptops, smartphones etc.).
Lithography is a technology used by chip manufacturers, which consists in transferring a shrunk geometrical pattern of circuit lines from a photomask to a wafer, by photomask illumination.
Conventional static resolution enhancement techniques are no longer sufficient when aiming for sub-32 nanometer minimum feature size, since dynamic optical path distortions become significant. For example, illumination scanning induces rapidly changing local in-plane and out-of-plane wafer deformations around the exposed area. This leads to unconformity between the projected image and the wafer surface.
To continue shrinking the minimum feature size, we are interested in compensating for the local heat-induced wafer deformations. A distributed actuation and sensing concept at the wafer stage is proposed and the implementation of fast and optimal control algorithms is investigated. It is expected that the above approach will contribute to the development of novel technologies in optical lithography that meet future requirements of sub-32 nanometer level feature size.
Image courtesy of ASML.